The present invention relates to a method and apparatus for providing DCFM capability in a signal generator and, in particular, to a frequency count and correct technique utilized with an unlocked phase-locked loop.
It is often desirable to have a signal generator which possesses the capability to perform like a voltage controlled oscillator, i.e., the signal generator output signal is dependent on an input voltage under operator control. This capability allows the operator not only to perform sweep-like measurements, but also allows frequency modulation (FM) of the output signal at very low rates, down to DC (thus the name DCFM).
It is known to provide an output signal variable over a given frequency range with a DCFM capability. One such signal generator comprises a frequency synthesizer utilizing one or more phase-locked loops (PLL). A PLL is in effect a control system that maintains a constant phase difference between two signals. Any variations in the phase of one signal relative to the other are removed by the PLL. This property of a PLL is utilized to suppress noise and clean up a signal; however, this property also tends to suppress any FM of the PLL output within the loop bandwidth. The loop must be modified in some way to allow DCFM. One technique is described in U.S. patent application Ser. No. 581,767, filed on Feb. 21, 1984, by Marcus K. DaSilva et al., entitled "Frequency Modulation in a Phase Locked Loop".
A second technique provides DCFM capability by opening--unlocking--the PLL and making the oscillator tune line available to the operator. The advantage of this technique is that it is simple, but the primary disadvantage is that a frequency offset in the output will occur when the loop is unlocked. Typically, the approach is to optimize the circuit hardware so as to minimize the frequency offset when the PLL is unlocked. This can be expensive and difficult to manufacture. The present invention solves the problem by allowing a relatively large frequency offset at the unlocked PLL and corrects for the frequency offset at another point in the frequency synthesizer.
The present invention includes a PLL capable of being unlocked and a three mode counter controlled by a 68000 microprocessor. When the operator selects external DCFM operation, the FM PLL is unlocked and the voltage controlled oscillator (VCO) tune line is made available to external control. Utilizing the counter, the exact frequency of the unlocked loop is determined. Since the desired frequency and the actual frequency of the VCO are known, the frequency error in the synthesizer output signal can be computed. An error signal is then provided to correct for the frequency change in the output frequency. The correction process takes about 250 milliseconds and is automatic whenever the operator requests the external DCFM mode.
The counter plus its associated hardware and software is also used for several additional functions: enhancement of internal audio frequency setting accuracy; continuous display of the actual output frequency of the synthesizer when in the DCFM mode; and correction of any VCO frequency drift during DCFM mode operation after the initial correction for the frequency change when the PLL was unlocked.